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In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10-12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 215 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ulpp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ulpp by applying PRBS data with a pattern length of 231 - 1.