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Low-voltage limitations of memory-rich nano-scale CMOS LSIs

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3 Author(s)
Kiyoo Itoh, B.S. ; Hitachi, Ltd., Tokyo ; Horiguchi, M. ; Yamaoka, M.

The low-voltage limitations of memory-rich nano- scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip- flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high- VDD bulk CMOS LSIs for low-cost low-standby-current applications and low-FDD FD-SOI LSIs for low-power applications.

Published in:

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Date of Conference:

11-13 Sept. 2007