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Architecture approaching the atomic scale

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1 Author(s)
Andre DeHon ; Department of Electrical and Systems Engineering, University of Pennsylvania, 200 S. 33rd St., Philadelphia, 19104, USA

Both bottom-up and top-down techniques have been used to fabricate assemblies of devices and interconnect where key, density-defining feature sizes are on the order of ten atoms wide. We show how complete computing architectures can be constructed from these new techniques and building blocks despite high defect rates, extreme regularity requirements, and statistical assembly. We further highlight the paradigm shifts in integrated circuit design and architecture which appear necessary to accommodate these atomic-scale effects. Our estimates suggest a 10 nm full-pitch FPGA-like design can achieve one to two orders of magnitude greater logic density than ideal, defect-free lithographic scaling to 22 nm.

Published in:

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Date of Conference:

11-13 Sept. 2007