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CAD Techniques for Power Optimization in Virtex-5 FPGAs

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4 Author(s)
Gupta, S. ; Xilinx Inc., San Jose ; Anderson, J. ; Farragher, L. ; Qiang Wang

We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007