CAD Techniques for Power Optimization in Virtex-5 FPGAs

We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinx® Virtex™-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.