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Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL, and its advanced verification capability, with C++ based system level language SystemC. The main contributions of this paper are (i) the integrated framework for model-driven development and validation of system-level designs with a combination of ESTEREL, and SystemC; and (ii) the test generation framework for generating test suites to satisfy traditional coverage metrics such as the statement and branch as well as a complex metric such as modified condition/decision coverage (MCDC) employed in the validation of safety-critical software systems. The framework also generates tests that attain functional coverage using properties specified in a temporal language and assertion-based verification (namely PSL). We demonstrate the methodology with a case study by developing and validating a critical power state machine component that is used for power management in embedded systems.