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New 3-D Chip Stacking Architectures by Wire-On-Bump and Bump-On-Flex

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5 Author(s)
Baik-Woo Lee ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA ; Jui-Yun Tsai ; Hotae Jin ; Chong K. Yoon
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Two new 3-D chip stacking technologies, wire-on-bump (WOB) and bump-on-flex (BOF), are proposed and demonstrated with their prototypes. The WOB and BOF technologies are for low cost 3-D stacking of memory chips by vertical side interconnections with metal wires and flex-circuits, respectively. These new 3-D chip stacking technologies have benefits such as a shorter signal path and 3-D stackability of an unlimited number of chips compared to wire-bonded chip stacking. In the case of the BOF technology, additional active and passive components can be either surface-mounted onto or embedded into the flex-circuit, which is an added value that other chip stacking technologies have not demonstrated so far. More importantly, the WOB and BOF technologies enable lower cost processes than Si through-via technology, which is thus more suitable for memory chip stacking. This paper describes the detailed processes for our unique chip stacking structures with vertical interconnection methods of the WOB and BOF. Finite-element modeling and thermal cycle (TC) tests are also performed to address their thermo-mechanical reliability.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:31 ,  Issue: 2 )