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Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

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2 Author(s)
Karthikeyan Reddy ; Indian Inst. of Technol., Chennai ; Shanthi Pavan

We examine noise due to clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators (CT-DSMs) employing nonreturn to zero (NRZ) feedback digital-to-analog converters (DACs). Using the discrete-time version of the Bode sensitivity integral, we derive a lower bound on jitter noise and its relationship to the noise transfer function (NTF) of the modulator. We show that NTFs with optimized zeros result in lower jitter noise than those with all zeros at the origin. We give intuition to a recent observation (arrived through numerical optimization) that NTFs with peaking in their passbands have lower jitter noise than maximally flat NTFs. We propose a design procedure that minimizes the sum of the quantization and jitter noise. The arguments regarding Delta Sigma analog-to-digital converters are extended to Delta Sigma DACs and measurement results are presented.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:54 ,  Issue: 10 )