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Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM

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24 Author(s)
Y. K. Park ; Advanced Technology Development, San #16, Banwoel-dong, Taean-Eup, Hwaseong-City, Kyungki-Do, Korea. Tel) 82-31-208-5390, Fax) 82-31-208-4799, E-mail) ; S. H. Lee ; J. W. Lee ; J. Y. Lee
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A 56 nm feature sized 1 Gb DRAM technology is successfully developed using ArF immersion lithography with a novel integration scheme. The cell size is 0.019 mum, which is the smallest one ever reported. In order to achieve high performance transistor characteristics with scaled down channel length, gate electrode is changed with dual poly tungsten metal gate, as well as elevated source-drain area with selective epitaxial growth (SEG) Si layer. For the data retention of DRAM cell, Asymmetric channel doping (ASC) is more localized through the data node contact of the cell transistor. High aspect ratio OCS structure and ZAZ dielectric scheme were developed for high cell capacitance.

Published in:

2007 IEEE Symposium on VLSI Technology

Date of Conference:

12-14 June 2007