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A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node

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5 Author(s)
Gen Tsutsui ; Advanced Device Development Division, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, JAPAN. Tel: +81-42-771-0707, Fax: +81-42-771-0952, e-mail: gen.tsutsui@necel.com ; Shinya Maruyama ; Tomohisa Abe ; Hidetatsu Nakamura
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Integration technique enabling Poly/Hf/SiON gate stack with four different thickness of SiON layer is demonstrated for the first time. Two advantages of hafnium dielectric introduction, which enable low cost integration, are discussed; (i) suppression of reverse narrow channel effect and (ii) sharing of ion implantation processes among core logic (transistors used in logic circuit) and I/O transistors. In addition, mobility improvement techniques by surface roughness and local stress reduction, which enable transistor performance boost with no cost addition, are discussed. These techniques realize highly cost-effective LOP/LSTP integrated CMOS platform for 45 nm node.

Published in:

2007 IEEE Symposium on VLSI Technology

Date of Conference:

12-14 June 2007