Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Lu, N.C.-C. ; AT&T Bell Lab., Allentown, PA, USA ; Sung, J.J. ; Yu, C.-H.D.

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5- mu m physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices.<>

Published in:

Electron Device Letters, IEEE  (Volume:10 ,  Issue: 11 )