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Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions

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3 Author(s)
C. -Y. Lu ; AT&T Bell Lab., Allentown, PA, USA ; J. J. Sung ; C. -H. D. Yu

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5- mu m physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices.<>

Published in:

IEEE Electron Device Letters  (Volume:10 ,  Issue: 11 )