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Notice of Violation of IEEE Publication Principles
"A 54 dBω + 42 dB 10 Gb s SiGe Transimpedance-Limiting Amplifier Using Bootstrap Photodiode Capacitance Neutralization and Vertical Threshold Adjustment"
by Maxim, A
in the IEEE Journal of Solid State Circuits, Vol. 42, No. 9, Sept. 2007, pp 1851-1864
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A high-gain 10 Gb/s transimpedance-limiting amplifier (TIA-LA) capable of directly driving a SERDES IC was realized in a 60 GHz fT 0.2 mum SiGe BiCMOS SOI process. The shunt-feedback common-emitter input stage uses a bootstrap technique to neutralize the photodiode parasitic capacitance. Cascode configurations and cross-coupled Miller capacitance cancellation were used to minimize the input capacitance of the signal path stages. This reduces the number of inter-stage isolation emitter- followers, allowing low-voltage operation. A signal-amplitude-dependent adjustable threshold was implemented- in the back-end limiting stages by using inverse hyperbolic tangent circuits. Integrating the high-gain TIA-LA signal path on the same die was made possible by using an SOI process in conjunction with die thinning to reduce substrate coupling and minimizing the output-to- input bondwire magnetic coupling through a careful pin location selection. The main limiting-TIA IC specifications include: 96 dBOmega total gain given by 54 dBOmega TIA gain and 42 dB LA voltage gain, 12 muA input sensitivity, < 8 pA/ radicHz input equivalent noise, 0.3 W power consumption from a 3.3 V supply and 1.8 times 1.8 mm2 die area.