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A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

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2 Author(s)
Zhimin Li ; Silicon Labs., Austin ; Fiez, T.S.

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 9 )

Date of Publication:

Sept. 2007

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