By Topic

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Srikanth Gondi ; Univ. of California, Los Angeles ; Behzad Razavi

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10-13 while consuming 133 mW from a 1.6-V supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:42 ,  Issue: 9 )