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This paper presents an error concealment processor to increase the performance of the TV receiver while the decoding bit stream over error-prone channel suffers from damage. An efficient error-concealment algorithm is advised with the adaptation of the spatial interpolation and the temporal prediction to reduce the nonmatched error for high motion regions and achieve fine resolution for still or low motion regions. Based on the adaptive algorithm, we proposed a parallel VLSI architecture with pipeline scheduling for real time implementation. The error concealment processor consists of the computational core, RAM block and interface, and then is integrated to the video decoder by using a complex processing schedule. The computational sources are commonly used for various frame types processing to reduce the hardware cost. The chip occupies about 27 k gates and includes one on-chip line-buffer. The silicon area is about 9 mm2 and the throughput rate can achieve 50 Mpixels/s, when implemented by 0.35-mum CMOS technology.
Circuits and Systems for Video Technology, IEEE Transactions on (Volume:17 , Issue: 8 )
Date of Publication: Aug. 2007