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We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.