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Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits

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4 Author(s)
Raychowdhury, A. ; Dept. of Electr. & Comput. Eng., Purdue Univ., IN ; Xuanyao Fong ; Qikai Chen ; Roy, K.

Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic. Analysis shows that this device can deliver 800times higher performance (@iso-IOFF) compared to a MOSFET. The possible use of this device as a sleep transistor in conjunction with the regular Si MOSFET shows 2000times average improvement in leakage power compared to Si MOSFETs

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006