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Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing

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2 Author(s)
Christopher S. Taillefer ; McGill University, 3480 University Street, Montreal, QC H3A 2A7 Tel: (514) 398-6029. E-mail: ; Gordon W. Roberts

A new architecture and signal processing methodology is proposed to implement a first-order single-bit delta-sigma (DeltaSigma) analog-to-digital converter (ADC). The proposed design converts an analog input voltage into a time-difference variable and performs the DeltaSigma signal processing in the time-mode. This offers an incredibly compact and low-power ADC solution while thriving in a low-voltage CMOS environment. The proposed design was fabricated in a standard 0.18-mum CMOS process occupying a silicon area of 15-mum times 25-mum and consumes 475-muW of power. Experimental results reveal that the design can provide a 7-bit resolution at a sampling rate of 140-MHz and input bandwidth of 400-kHz.

Published in:

2007 IEEE International Symposium on Circuits and Systems

Date of Conference:

27-30 May 2007