Referenced Items are not available for this document.
This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade SigmaDeltamodulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.
Published in:
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Date of Conference: 27-30 May 2007
- Page(s):
- 1 - 4
- E-ISBN :
- 1-4244-0921-7
- Print ISBN:
- 1-4244-0920-9
- INSPEC Accession Number:
- 9538965
- Conference Location :
- New Orleans, LA
- Digital Object Identifier :
- 10.1109/ISCAS.2007.378128
- Product Type:
- Conference Publications
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