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Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

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4 Author(s)
Ray, S. ; IBM Integrated Supply Chain, Hopewell Junction ; Muncy, J. ; McLaughlin, P.V. ; Nicholls, L.

In this paper, the the authors summarise Sn/Ag Pb-free plated bumps that have been qualified for low-k 65 nm technology on thin-core build-up laminates. The bump pitch is 200 mum, and the laminate size is 42.5 mm. One of the key issues addressed in this qualification was whether Pb-free bumps along with assembly to build-up laminates with thin-core result in enough stress to cause any low-k related fails such as delamination or cracks in the low-k wiring layers. In IBM this is carried out with special wiring and via-chains on the test-die that are monitored after assembly to package, and through reliability testing-perimeter lines, and delamination sensors, serpentines, and via-chains on the test-die that are tested for continuity and isolation of individual nets. These structures survive wafer-level stressing, and fails in modules are due to additional stress or damage induced by the bond and assembly processes.

Published in:

Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th

Date of Conference:

May 29 2007-June 1 2007