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A 50nm high-k poly silicon gate stack with a buried SiGe channel

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13 Author(s)
S. Jakschik ; Infineon, Kapeldreef 75 B-3001 Heverlee, Belgium; ; T. Hoffmann ; H. -J. Cho ; A. Veloso
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This report presents high-k poly ring oscillators with a performance of tau=16.2 ps/st at 6E-6A/st for Lg=80 nm. This was achieved by using a SiGe channel for nFET and pFET. A minimum device length of 50 nm was built by using this technique. The transistors reach Ion=120 muA/mum at Ioff=20 pA/mum with Tinv=2.4 nm, resulting in a normalized delay of 8.7 ps (Vdd=1.0 V). This is the best high-k poly pFET performance published so far (~Ion=220 muA/mum at Vdd=-1.2 V). We demonstrate the combination of the SiGe channel with common performance enhancement techniques like stress liners and rotated channel as used in the hybrid oriented substrate technique. The buried channel improves short channel effects and has no reliability trade off. Although hole mobility is enhanced in SiGe channel transistors, further gain was observed in narrow width structures. Peak mobility can be up to 130 cm2/Vs for pFET, extending the universal mobility for silicon. After investigating Vt and short channel effects we are able to show, that half of the gain is caused by more efficient stress in narrow width structures. The other half is attributed to EPI loading effects in small structures. Fluorine I/I in the well improves NBTI behavior by more than one decade in time.

Published in:

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Date of Conference:

23-25 April 2007