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Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

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7 Author(s)
Lin, Hao ; Sch. of Appl. & Eng. Phys., Cornell Univ., Ithaca, NY ; Liu, Haitao ; Kumar, A. ; Avci, Uygar
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We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 6 )

Date of Publication:

June 2007

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