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A Top-Down Approach to Architecting CPI Component Performance Counters

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4 Author(s)

Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various miss events. Constructing accurate CPI components for out-of-order superscalar processors is complicated, however, because computation and miss event handling overlap. The authors' counter architecture, using an analytical superscalar performance model, handles overlap effects more accurately than existing methods

Published in:

IEEE Micro  (Volume:27 ,  Issue: 1 )