By Topic

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Amory, A.M. ; Inst. de Informatica, Fed. Univ. of Rio Grande do Sul, Porto Alegre ; Goossens, K. ; Marinissen, E.J. ; Lubaszewski, M.
more authors

A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated test access mechanism (TAM), such as a TestRail or test bus. The approach leaves both the tester, as well as the embedded core and its test unchanged, while the functional interconnect can handle the test data transport as a regular data application. The functional interconnect is required to offer guaranteed throughput and zero latency variation, a service that is available in many buses and networks. For 672 example cases based on the ITC'02 System-on-Chip (SOC) Test Benchmarks, the new approach in comparison with the conventional approach shows an average wrapper area increase of 14.5%, which is negligible at the SOC level, especially since the dedicated TAM can be eliminated. Furthermore, the new approach decreases the core test length by 3.8% on average

Published in:

Computers & Digital Techniques, IET  (Volume:1 ,  Issue: 3 )