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This paper presented an inverter based 3rd order sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancellation. The ADC has been implemented in TSMC 2P6M 0.18 μm CMOS technology with a core area of 0.54 mm2. The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42 μW and the dynamic range of 66.02 dB.