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A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

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3 Author(s)
Huei-Yan Huang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Jun-Chau Chien ; Liang-Hung Lu

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mum CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10-12 are 300 and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68times0.8 mm2 where the active circuit area only occupies 0.32times0.6 mm2

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 5 )