Referenced Items are not available for this document.
This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power consumption is 33 mW
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:42
,
Issue:
4
)
Date of Publication: April 2007
- Page(s):
- 757 - 765
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9392288
- Digital Object Identifier :
- 10.1109/JSSC.2007.891683
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 26 March 2007
- Issue Date :
- April 2007
- Sponsored by :
- IEEE Solid-State Circuits Society
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