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Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

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1 Author(s)
Mark B. Josephs ; London South Bank University, UK

FDR (failures-divergences refinement) is a tool for verifying properties of processes expressed in a machine-readable dialect of CSP (CSPM). This paper shows how to model asynchronous logic blocks as processes in CSPM and how to verify them using FDR: processes abstract away from the speed of the blocks; multi-way synchronization facilitates the modelling of isochronic forks; receptiveness is formalised as an assertion for FDR to check; process trans formations allow one to model transmission lines and handshaking ports. A process parameterised by a Boolean function suffices to model any complex gate; another such process models N-way mutual exclusion. The approach is illustrated on a variety of asynchronous circuits drawn from the literature.

Published in:

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

Date of Conference:

12-14 March 2007