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Design of a High-Speed Asynchronous Turbo Decoder

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4 Author(s)
Pankaj Golani ; University of Southern California, Los Angeles ; Georgios D. Dimou ; Mallika Prakash ; Peter A. Beerel

This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limited-bandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous high-speed turbo decoder that can be potentially used for new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using a new static single-track-full-buffer (SSTFB) standard cell library in IBM 0.18 mum technology that provides low latency, fast cycle-time, and more robustness to noise than previously studied single-track full-buffer technology (STFB). A high-speed synchronous counterpart using the same high-speed architecture is designed in the same technology for comparison. The results demonstrate that for a variety of network constraints, the asynchronous design provides advantages in throughput per area. Moreover, the asynchronous design can support very low-latency network constraints not achievable with the synchronous alternative.

Published in:

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

Date of Conference:

12-14 March 2007