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Chip-to-Board Micromachining for Interconnect Layer Passive Components

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2 Author(s)
Yeun-Ho Joung ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA ; Mark G. Allen

Integrated inductors are typically formed either on a chip or embedded in a package or board. In this work, we explore the possibility of forming inductors in the chip-to-board interconnect layer. The solderless technique of copper (Cu) electroplating bonding is used to simultaneously form inductor structures as well as chip-to-board interconnect. The use of the gap between the chip and substrate for inductors not only increases integration density, but also allows large magnetic cross-sectional areas to be achieved. To demonstrate the technology, a plating-through-mold method has been used in the establishment of tall interconnect or solenoid inductors. For demonstration of the electroplating bonded micro solenoid structures, three- and seven-turn (500mum in height) inductors have been realized with measured inductances of 3.6 and 10.4nH, and Q-factors of 71 and 55, respectively. As an alternative approach, a polymer-core-conductor method in which polymer posts coated with metal are electroplating bonded, has been developed. This approach reduces processing time in the fabrication of the tall metal structures. For the polymer core RF structures, three-, five-, seven-, and 10-turn inductors have been fabricated. These inductors have inductances of 4.2, 7.0, 9.6, and 13.6nH, and Q-factors of 72, 64, 56, and 61, respectively

Published in:

IEEE Transactions on Components and Packaging Technologies  (Volume:30 ,  Issue: 1 )