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Design of Digital Audio DSP Core

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6 Author(s)
Chang Won Ryu ; Dept. of Electr. Eng., Pusan Nat. Univ., Busan ; Dong Hun Lee ; Hua Jun Chi ; Kyoung Su Kwan
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This paper describes the architecture and design procedure of a DSP (digital signal processor) for the digital audio applications. The suggested DSP has fixed 24bit data structure, 6 stage pipeline, and 127 instructions. Some of the instructions are specially designed for the audio signal processing. Almost instructions are completed within a single cycle. The designed DSP has been verified by comparing the results from CBS (cycle based simulator) and those of HDL simulation through the single instruction set test and the instruction combination test, and real audio applications. Finally, we confirm by the HDL simulation that the DSP carried out successfully out ADPCM and MPEG-2 AAC decoding algorithm. The DSP core is implemented in FPGA using ALTERA Excalibur device and operates at 4MHz.

Published in:

Strategic Technology, The 1st International Forum on

Date of Conference:

18-20 Oct. 2006

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