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A QCA Implementation of a Configurable Logic Block for an FPGA

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2 Author(s)
Lantz, T. ; Dept. of Electr. Eng., Rochester Inst. of Technol., NY ; Peskin, E.

This paper presents the design, layout, and successful simulation of a configurable logic block (CLB) for a field-programmable gate array (FPGA) architecture based on a next-generation technology, quantum-dot cellular automata (QCA). Previous work on QCA-based FPGAs has focused on programmable interconnect. In contrast, this paper focuses on programmable logic. A novel single-layer CLB with fixed interconnect is developed by implementing four look-up tables (LUTs). Also, this paper presents a novel serial write/random-access read QCA memory design, which is one of the components in a LUT QCADesigner software is used to design and simulate a 4-to-16 decoder, 16-bit memory, and output circuit to implement a LUT. The simulation of the CLB confirms the expected outcomes

Published in:

Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on

Date of Conference:

Sept. 2006