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Design Trade-offs for Low-power and High Figure-of-merit LNA

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5 Author(s)
Hsien-ku Chen ; National Chip Implementation Center, National Applied Research Laboratories, 7F, No.26, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu 300, Taiwan, Republic of China ; J. R. Sha ; Da-chiang Chang ; Ying-zong Juang
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We report a 5.4 mW ultra low dc power low noise amplifier (LNA) at 5.5 GHz, which is based on a 0.35-mum BiCMOS technology. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the usage of the HBT-cascade-MOS methodology is simultaneously satisfied the tradeoff between noise figure (NF) and linearity of LNA. This amplifier achieves a gain/(NF times PDC ) ratio figure of merit of 0.774 (1/mW) which is the better reported at 5~6-GHz band and suitable for wireless LAN applications

Published in:

2006 International Symposium on VLSI Design, Automation and Test

Date of Conference:

26-28 April 2006