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A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications

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2 Author(s)
Zhih-Siou Cheng ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., HsinChu ; Jenn-Chyou Bor

A 64 dB gain range VGA with DC offset calibration loop is proposed in this work. This VGA adopts the degeneration type amplifier to vary voltage gain and uses the super-source-follower input stage to enhance the linearity. A digital-based DC offset calibration loop is also designed to solve the DC offset problem. An experimental chip is fabricated in 0.18 mum process. With 2 dB step, the gain error is less than 0.8 dB and the output DC offset is less than 100mV at maximum gain setting. The total power consumption is 11 mW

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006

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