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A Low Power Mobile Camera Processor Design with SubLVDS Interface

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3 Author(s)
Charng L. Lee ; Sunplus Technology Co., Ltd., 19 Innovation First Rd, Science Park, Hsinchu, 300 Taiwan, R.O.C. ; Kuang-ting Hsiao ; Min-chung Chou

A mega pixel image signal processor (ISP) with low voltage differential serial interface is presented. subLVDS interface has lower voltage swing and lower power consumption advantages over a normal LVDS interface. Both subLVDS driver and receiver are implemented in this ISP chip to reduce the I/O pin count. A synchronization layer is designed to cover both non-compressed and compressed image data transfer on the high-speed serial data link. This chip is designed with a pure logic process in 0.18 mum CMOS technology. The subLVDS driver can operate at a transfer rate up to 625Mbps

Published in:

2006 International Symposium on VLSI Design, Automation and Test

Date of Conference:

26-28 April 2006