By Topic

Reconfigurable Shuffle Network Design in LDPC Decoders

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tang, J. ; Univ. of Minnesota, Twin Cities, MN, USA ; Bhatt, T. ; Sundaramurthy, V. ; Parhi, K.K.

Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. This paper proposes an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.

Published in:

Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on

Date of Conference:

11-13 Sept. 2006