By Topic

Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Massimo Alioto ; Dipt. di Ingegneria dell'Informazione, Siena Univ. ; Rosario Mita ; Gaetano Palumbo

A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the power-delay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18-mum CMOS process

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:53 ,  Issue: 11 )