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A field programmable accelerator for compiled-code applications

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3 Author(s)
Lewis, D.M. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; van Ierssel, M.H. ; Wong, D.H.

Describes a special-purpose application accelerator using field-programmable gate arrays to accelerate a range of applications. The accelerator is designed to support applications by allowing the user to implement a processor with an instruction set designed for the specific application being accelerated, using specialized instructions to implement critical fragments of the application. A compiled-code software organization is used to reduce overhead operations. A prototype has been built, and the first application to be ported to it, logic simulation, is underway

Published in:

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Date of Conference:

3-6 Oct 1993