Referenced Items are not available for this document.
This paper introduces and evaluates functional fault models for test pattern generation of sequential circuits at the finite state machine level. Evaluation of the proposed fault models against their gate level fault coverage on multi-level implementations is presented. The relationships between functional and gate level fault coverage are discussed
Published in:
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Date of Conference: 3-6 Oct 1993
- Page(s):
- 572 - 575
- Meeting Date :
- 03 Oct 1993-06 Oct 1993
- Print ISBN:
- 0-8186-4230-0
- INSPEC Accession Number:
- 4955936
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1993.393312
- Product Type:
- Conference Publications
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