Numerical simulation of single event latchup in the temperature range of 77-450 K

In this paper, the temperature dependence of single event latchup in CMOS structures is studied over a temperature range of 77-450 K through two-dimensional device simulation with full-temperature models. Single event latchup immunity first increases as the temperature decreases from 450 K to 120 K, and then decreases rapidly with further decrease in temperature. Therefore, superior latchup immunity can be expected at about 120 K. Furthermore, latchup immunity at 77 K is almost equal or somewhat inferior to that at room temperature. It can be predicted from our results that CMOS devices become extremely susceptible to single event latchup at temperatures below 77 K just as they do at very high temperatures