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Browse Conference Publications > Design Automation, 1993, with ... Help

VERTEX: VERification of Transistor-level circuits based on model EXtraction

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4 Author(s)
Moondanos, J. ; Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA ; Wehbeh, J.A. ; Abraham, J.A. ; Saab, D.G.

VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware design by employing novel techniques to extract the relevant state variables of a switch-level circuit and to compare the finite state machine descriptions of hardware designs based on formal methods for the verification of sequential circuits

Published in:
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference: 22-25 Feb 1993

Page(s):
111 - 115
Meeting Date :
22 Feb 1993-25 Feb 1993
Print ISBN:
0-8186-3410-3
INSPEC Accession Number:
4885155
Conference Location :
Paris
Digital Object Identifier :
10.1109/EDAC.1993.386491
Product Type:
Conference Publications

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