By Topic

VERTEX: VERification of Transistor-level circuits based on model EXtraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
J. Moondanos ; Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA ; J. A. Wehbeh ; J. A. Abrahamn ; D. G. Saab

VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware design by employing novel techniques to extract the relevant state variables of a switch-level circuit and to compare the finite state machine descriptions of hardware designs based on formal methods for the verification of sequential circuits

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993