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Bit-alignment in hardware allocation for multiplexed DSP architectures

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3 Author(s)
K. Schoofs ; IMEC, Leuven, Belgium ; G. Goossens ; H. De Man

Finding a correct mapping of the bits of every signal onto the bit lines of a connection or operator terminal of multiplexed VLSI architectures is considered. An approach to solve alignment problems that occur in this mapping process is presented. Bit alignment is an essential element of the hardware allocation process for DSP applications. The result is a bit-true silicon compiler, which is able to implement every signal type exactly as specified in the behavioral description. This approach is exemplified with a case study

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993