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Architectural-level fault simulation using symbolic data

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3 Author(s)
J. Lee ; Center for Reliable & High-Performance Comput., Univ. of Illinois, Urbana, IL, USA ; E. M. Rudnick ; J. H. Patel

A fault simulation technique which uses architectural-level information is proposed. This approach allows one to simulate stuck-at faults in specific modules within the context of the overall design. Gate-level descriptions of all modules are not required, so this method can be applied early in the design phase. At the architectural level, the behavioral simulation uses symbolic data to simultaneously process the fault effects for groups of faults in the module under simulation in order to achieve speedup. The proposed techniques have been implemented, and several circuits described at a high level have been simulated successfully using different test sets

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993