By Topic

An approach to scheduling and allocation using regularity extraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Rao, S.D. ; Dept. of Electr. & Comput. Eng., Univ. of California, Irvine, CA, USA ; Kurdahi, F.J.

The authors propose that an important class of VLSI systems that are characterized by regularity of their descriptions can be efficiently synthesized in a hierarchical fashion. In other words, the regularity can be extracted to abstract the system design, thereby simplifying the complex tasks of behavioral synthesis. Heuristics that extract regularity and explore the design space in a hierarchical fashion are presented and the feasibility of the approach on signal processing systems is demonstrated. Extension of the proposed approach to other synthesis tasks is being investigated

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993