Technology decomposition using optimal alphabetic trees

A technique for converting an arbitrary sum-of-products expression into a subnetwork of two-input NAND gates such that, given a fixed linear order on the inputs to the expression, the signal arrival time at the output of the subnetwork is minimum, is presented. The procedure, which is based on an algorithm for constructing optimal binary trees for alphabetic codes, is optimal for complex nodes with sum-of-products expressions having noncrossing literal support. This procedure has been said to recursively NAND-decompose a Boolean network based on the input ordering information derived from a companion placement solution resulting in reduced chip area and improved performance after technology mapping, placement and routing