Referenced Items are not available for this document.
In multimedia digital video applications, international standards such as JPEG, MPEG, and H.261 are widely adopted. Many DSP architectures have been proposed to meet requirements on the digital video. In this paper, a static data flow architecture containing nine parallel processors is described. Each processor made with a specialized hardware engine such as DCT and quantizer operates asynchronously and independently on its own data presence. This proposed DSP is fabricated in a 0.8 μm triple metal technology with 16×16 mm2 die area over 1.5 million transistors. The peak computing capability over 1 billion operations per second can provide full programmability for any DCT based digital video compression standards
Published in:
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Date of Conference: 1-4 May 1994
- Page(s):
- 103 - 106
- Meeting Date :
- 01 May 1994-04 May 1994
- Print ISBN:
- 0-7803-1886-2
- INSPEC Accession Number:
- 4903503
- Conference Location :
- San Diego, CA
- Digital Object Identifier :
- 10.1109/CICC.1994.379757
- Product Type:
- Conference Publications
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