By Topic

Data flow processor for multi-standard video codec

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Lee, B.W. ; DSP Technol. Center, Samsung Electron. Co., KyungGi-Do, South Korea ; Kwon, H.S. ; Kim, B.N. ; Still, D.
more authors

In multimedia digital video applications, international standards such as JPEG, MPEG, and H.261 are widely adopted. Many DSP architectures have been proposed to meet requirements on the digital video. In this paper, a static data flow architecture containing nine parallel processors is described. Each processor made with a specialized hardware engine such as DCT and quantizer operates asynchronously and independently on its own data presence. This proposed DSP is fabricated in a 0.8 μm triple metal technology with 16×16 mm2 die area over 1.5 million transistors. The peak computing capability over 1 billion operations per second can provide full programmability for any DCT based digital video compression standards

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994