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A 10-bit, 20-MS/s, 35-mW pipeline A/D converter

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2 Author(s)
T. B. Cho ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; P. R. Gray

This paper describes a 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include operation on a 3.3 V power supply, optimum scaling of capacitor values through the pipeline, and digital correction to allow the use of dynamic comparators. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR for 100 kHz input at 20 MS/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994