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Parallel delta-sigma A/D conversion

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4 Author(s)
King, E. ; Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA ; Aram, F. ; Fiez, T. ; Galton, I.

This paper presents an architecture wherein multiple delta-sigma modulators are combined so that neither time oversampling nor time interleaving are necessary. For a system containing M Pth-order delta-sigma modulators, approximately P bits of accuracy are gained for every doubling of M. Thus, the resolution gained by combining M delta-sigma modulators is approximately the same as that with the same modulator with an oversampling rate of M. Measured results from a 16-channel parallel delta-sigma A/D converter composed of second-order delta-sigma modulators verify the theory and demonstrate that this architecture retains much of the robustness of the individual delta-sigma modulators to non-ideal circuit behavior

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994