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The Gauss machine: A Galois-enhanced quadratic residue number system systolic array

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3 Author(s)
J. D. Mellott ; High Speed Digital Archit. Lab., Florida Univ., FL, USA ; J. C. Smith ; F. J. Taylor

The Gauss machine is a SIMD systolic array architecture that takes advantage of the Galois-enhanced residue number system (GEQRNS) to form reduced-complexity arithmetic elements. The Gauss machine is targeted at front-end signal and image processing applications. A discrete prototype that achieves a peak rating of 320 million complex arithmetic operations per second while operating at 10 MHz has been constructed. A VLSI implementation of the Gauss machine's processor cell has been created. The VLSI implementation is implemented in 2.0-μm CMOS and achieves greater than 20-MHz performance, using less than 2.0-mm2 die area. It is shown that techniques for defect tolerance in RNS systolic arrays can result in substantial yield enhancement, thereby making larger than conventional (ULSI) systems possible

Published in:

Computer Arithmetic, 1993. Proceedings., 11th Symposium on

Date of Conference:

29 Jun-2 Jul 1993