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A wide-bandwidth low-voltage PLL for PowerPC microprocessors

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4 Author(s)
J. Alvarez ; Somerset Design Center, Motorola Inc., Austin, TX, USA ; H. Sanchez ; G. Gerosa ; R. Countryman

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 4 )